Tutorial A-C: Behavioral and System-Level VHDL
Speaker
- Wolfgang Ecker: Siemens AG, Corporate Research and Development
Abstract
VHDL is widely used in the current design process. It is mainly applied
for modeling, specification and simulation on Gate- and RT-Level. In
this tutorial, VHDL aspects useful for behavioral modeling are taught.
First all related VHDL features are repeated, namely: time model, driver
model, hierarchy model and access types. Additionally abstraction in context
of modeling and design is defined, classified and related to VHDL features.
The term "behavioral modeling" is also discussed in this context.
Modeling of monitors and communication mechanisms, well known from operating
system theory, are covered then in the first VHDL modeling related part. The
second part coming next deals with abstract data types as known from software
engineering. Afterwards a communication scheme for variant length data
is presented. Both, communication mechanisms and abstract data types are
combined in this application.
Finally a set of application domains for the modeling techniques are shown.
Attendees
Advanced VHDL users.
ifip@it.uc3m.es