In cooperation with: CICYT and University of Cantabria
Sunday, April 20
9h T1: Formal Methods in Hardware Design
M. Broy, Technical University of Munich
B. Möller, University f Augsburg
N. Harman, University of Wales
J. Bergstra and A. Ponse, Univ. of
Amsterdam
9h T2: VHDL Lite - How VHDL Can Be Slimmed Down
S. Krolikoski, Cadence Design Systems
O. Levia, Cadence Design Systems
C. Ussery, Cadence Design Systems
9h T4: VLSI embedded system design
S. Olcóz, SIDSA
C. Navarro, SIDSA
9h T6: Methods of PSPICE analog, digital and mixed behavioral macromodeling of electronic devices and circuits
D. Andreu, ENSEEIH-INP
14h30m T3: The IEEE Standard VHDL Synthesis Packages: IEEE Std 1076.3-1996
J. Bhasker: Lucent Technologies
14h30m T5: Quality-driven design of electronic systems
L. Jozwiak, Eindhoven University of
Technology
14h30m T7: Behavioral and system-level VHDL
W. Ecker, SIEMENS
14h30m T8: VHDL 1076.1 through examples
A. Vachoux, Ecole Fed. Polytechnic de Laussane
Tuesday, April 22
Session 1: Code reusability
Chair: Eugenio Villar, University of Cantabria
9h Opening remarks
9h10m Synthesis interoperability and its impact on code reusability (invited speech)
J. Bhasker, Lucent Technologies
9h50m VHDL reusability (invited speech)
Y. Torroja, Polytechnic University
of Madrid
10h30m
Coffee Break
Session 2: Industrial applications
Chair: J. Uceda, Polytechnic University of Madrid
11h Modeling of a communication controller for real-time applications,
M. Sprachmann and H. Grünbacher, Technishe Universität Wien
11h30m A radiation hardened microcontroller for embedded space applications: A VHDL design at system and ASIC levels
X. Lobao and J. Sempere, INDRA Espacio
M. Moré, E. Lecha and Ll. Terés, CNM
12h A VHDL implementation of a digital modem for LEO satellite communication
E. Corominas, N. Simon and C. Ferrer, CNM
12h30m Methodologies in the design of an ASIC for AC drive control
P. Foussier and J.P. Chante, ECPA-CEGELY
X. Jordá, CNM
J. Carrabina, Universidad Autónoma
de Barcelona
13h
Lunch Break
14h30m Panel 1: Reusability and IPRs of VHDL models
Chair: Serafín Olcóz,
SIDSA
Session 3: Analog and power simulation
Chair: A. Vachoux, Ecole Federal Polytechnic de Laussane
16h30m Statistical modeling and simulation of ICs utilizing behavioral simulators and analog HDLs
J.F. Swidzinski and M.A. Styblinski, Texas Univ.
17h Mixed-signal modeling in VHDL by distributed local iteration
M. Schubert, Fachhochschule Regensburg
17h30m VHDL power simulator: Power analysis at gate level
L. Kruse, D. Rabe and W. Nebel, Univ.
Oldenburg
Wednesday, April 23
Session 4: Design verification and fault modeling
Chair: D. Borrione, ARTEMIS
9h Building testbenches under specification changes
L. Entrena, J.A. Espejo and E. Olías, Carlos III University of Madrid
9h30m Estimation of the quality of design validation experiments based on error models
T. Riesgo, Y. Torroja, C. López and J. Uceda, Polytechnic University of Madrid
10h VHDL modeling of bridging defects in CMOS integrated circuits
M. Santos, N. Vicente, M.B. Santos
and J.P. Teixeira, INESC
10h30m
Coffee Break
Session 5: Telecommunication applications
Chair: P. Plaza, TI+D
11h A CRC Verilog description module for a hard real-time communication protocol in a control distributed system,
J. Pérez, S. Felici and J.M. Insenser, SIDSA
11h30m VHDL design of a coder/decoder MICDA module up to 32 duplex channels
J.M. Hernández and J. Amengual, ALCATEL
12h The use of VHDL in the design of a digital filter for wireless communications
E. Lecha, J. Vidal and L. París, CNM, P. Aguayo, CIEMAT and R. Burriel, ALCATEL
12h30m Case-based synthesis of telecommunication architectures
L. Chaouat, A. Schmid, A. Vachoux
and D. Mlynek, Ecole Federal Polytechnic de Lausanne
13h Lunch Break
14h30m
Social Event
Thursday, April 24
9h Session 6: OMI: The European Systems Approach to Microprocessor Design and Application
Chair: Frank Cunningham,
European Commission
10h30m
Coffee Break
Session 7: System-level design
Chair: D. Sciuto, Politecnico de Milano
11h Comparing ADAí95 and VHDL for behavioral description on causal and synchronous level,
J. Böttger and W. Ecker, SIEMENS
11h30m OO extensions to VHDL, the LaMI proposal
J. Benzakki and B. Djafri, Université díEvry
12h Experiences in using several VHDL semantics to DSP systems: An architectural view
X. Warzee and S. Lasserre, THOMSON-CSF
12h30m A VHDL-based HW/SW co-design approach
J.F. Pérez, O. Cazorla, J.C.
Bordón and A. Suárez, University of Las Palmas
13h
Lunch Break
Session 8: FPGA design
Chair: W. Ecker, SIEMENS
14h30m VHDL modeling of fast dynamic reconfiguration on novel multicontext RAM-based FPDs
J. Faura, J.M. Moreno, J. Madrenas and J.M. Insenser, SIDSA
15h Fault-tolerant VHDL architectures for space applications
F. Alcalá, L. Berrojo and F. Ortega, ALCATEL-Espacio
15h30m FPGA rapid prototyping of ASPs
M. Gschwind, V. Salapura and D. Maurer,
Technishe Universität Wien
16h
Coffee Break
16h30m Panel 2: Which HDL to use for system design ?
Chair: S. Krolikoski, CADENCE