Advanced Programme for CHDL'97
Committees |
Registration Information |
Transportation Information |
Tourist Information
Tutorials
Morning Tutorials
- Tutorial M-A
- M. Broy, N. Harman, B. Möller, A. Ponse: Formal
Methods in Hardware Design
- Tutorial M-B
- S. Krolikoski, O. Levia, C. Ussery: VHDL Lite - How VHDL Can Be
Slimmed Down
- Tutorial M-C
- S. Olcoz, I. Hidalgo: VLSI Embedded System Design
- Tutorial M-D
- D. Andreu: Methods of PSPICE Analog, Digital and Mixed Behavioral
Macromodeling of Electronic Devices and Circuits
Afternoon Tutorials
- Tutorial A-A
- J. Bhasker: The IEEE Standard VHDL Synthesis Packages: IEEE Std
1076.3-1996
- Tutorial A-B
- L. Jozwiak: Quality-driven Design of Electronic Systems
- Tutorial A-C
- W. Ecker: Behavioral and System-Level VHDL
- Tutorial A-D
- A. Vachoux: VHDL 1076.1 through Examples
Presentations
- Session C-1: Specification
and Design of Reactive Systems
Chair: Luc Claesen, IMEC, Belgium
E. Cerny (Programme Chair), C. Delgado Kloos (General Chair): Opening
Remarks
G. Berry: Synchronous Languages for Hardware and Software Reactive Systems
(Invited Talk)
B. Kleinjohann, J. Tacken, Ch. Tahedl: Towards a Complete Design
Method for Embedded Systems Using Predicate/Transition-Nets
- Session C-2: Verification
Using Model Checking Techniques (+ Poster
Presentations)
Chair: Thomas Kropf, Karlsruhe Univ., Germany
F. Balarin, K. Sajid: Simplifying Data Operations for Formal Verification
K. Schneider: CTL and Equivalent Sublanguages of CTL*
R. Hojati, D. Dill, R.K. Brayton: Verifying Linear Temporal Properties
of Data Insensitive Controllers Using Finite Instantiations
C.-T. Chou, J.-L. Huang, M. Fujita: A High-Level Language for Programming
Complex Temporal Behaviors and its Translation into Synchronous Circuits
J. Philipps, P. Scholz: System-Level Hardware Design with µ-Charts
M. Auguin, C. Belleudy, G. Gogniat: Interface Synthesis in Embedded
Hardware-Software Systems
J.-P. Soininen, J. Saarikettu, V. Veijalainen, T. Huttunen: TripleS
- A Formal Validation Environment for Functional Specifications
R.J. Machado, J.M. Fernandes, A.J. Proença: SOFHIA: A CAD Environment
to Design Digital Control Systems
A. Bardsley, D. Edwards: Compiling the Language Balsa to Delay Insensitive
Hardware
C. Mandal, R.M. Zimmer: High-Level Synthesis of Structured Data Paths
- Session C-3: Formal
Characterizations of Systems
Chair: Ganesh Gopalakrishnan, Utah Univ., USA
K. Thirunarayan, R. Ewing: Charaterizing a Portable Subset of Behavioural
VHDL-93
B. Berkane, S. Gandrabur, E. Cerny: Algebra of Communicating Timing
Charts for Describing and Verifying Hardware Interfaces
F. Corella, R. Shaw, C. Zhang: A Formal Proof of Absence of Deadlock
for any Acyclic Network of PCI Buses
- Session C-4: Analog Languages
Chair: Wolfgang Nebel, Oldenburg Univ., Germany
V. Moser, H.-P. Amann, F. Pellandini: Behavioural Modelling of Sampled-Data
with HDL-A and ABSynth
Panel: Analog and Mixed-Signal HDLs
-
Moderator: Bart Romanowicz, EPF Lausanne, Switzerland
Panelists:
- Ernst Christen, Analogy, USA
- Mark Kahrs, Rutgers Univ., USA
- Joannis Papanuskas, Bosch, Germany
- Alain Vachoux, EPF Lausanne, Switzerland
- Session C-5: Languages in
Design Flows
S. Raghvendra (Synopsys): Hardware Description Languages in Practical
Design Flows (Invited Talk)
J.-M. Daveau, G. Fernandes Marchioro, A.A. Jerraya: VHDL Generation
from SDL Specification
B. Landwehr, P. Marwedel, I. Markhof, R. Dömer: Exploiting Isomorphism
for Speeding Up Binding in an Integrated Scheduling Allocation and Assignment
Approach to Architectural Synthesis (Short Talk)
- Session C-6: HDLs for the
XXI Century
Panel: The Next HDL Paradigms?
-
Moderator: Carlos Delgado Kloos, Univ. Carlos III de Madrid, Spain
Panelists:
- Gerard Berry, CMA, France
- Manfred Broy, Tech. Univ. München, Germany
- Stan Krolikoski, Cadence Design Systems, USA
- Wolfgang Nebel, Univ. Oldenburg, Germany
- Franz Rammig, Univ. GH Paderborn, Germany
- Srinivas Raghvendra, Synopsys, USA
- Session C-7: Formal
Methods for Asynchronous and Distributed Systems
Chair: Bernhard Möller, Augsburg Univ.
F. Corella: The World of I/O: A Rich Application Area for Formal Methods
(Invited Talk)
H. Barringer, D. Fellows, G. Gough, A. Williams: Abstract Modelling
of Asynchronous Micropipeline Systems using Rainbow
R. Nalumasu, G. Gopalakrishnan: A New Partial Order Reduction Algorithm
for Concurrent System Verification (Short Talk)
- Session C-8: Future Trends
in Hardware Design
(+ Poster Display)
Chair: Franz Rammig, Paderborn Univ., Germany
C. Ussery, S. Curry: Design and Verification Flows for Large Systems
in Silicon (Special Talk)
M. Heuchling, W. Ecker, M. Mrva: The Shall Design Test Development
Model for Hardware Systems
J. Mountjoy, P. Hartel, H. Corporaal: Modular Operational Semantic
Specification of Transport Triggered Architectures
- CHDL'97 Papers in
Sessions of the VHDL Users' Forum in Europe
L. Kruse, D. Rabe, W. Nebel: VHDL Power Simulator: Power Analysis at
Gate Level
J. Benzakki, B. Djafri: Object Oriented Extensions to VHDL. The LaMI
Proposal
Color Key for Presentations
Opening Remarks (15 min.)
Invited Presentation (45 min.)
Special Presentation (30 min.)
Regular Presentation (30 min.)
Short Presentation (15 min.)
Poster Presentation (5 min.)
Panel Session
Preliminary Conference Structure
Time for Tutorials |
Su, 20 April |
Mo, 21 April |
Tu, 22 April |
We, 23 April |
Th, 24 April |
Fr, 25 April |
Time for Conference |
|
9:00-13:30 |
Morning Tutorials |
C-1 |
V-1 |
N-3 |
V-4 |
C-7 |
L-1 |
V-6 |
L-3 |
|
L-7 |
9:00-10:30 |
C-2 |
V-2 |
N-4 |
V-5 |
C-8 |
L-2 |
V-7 |
L-4 |
|
L-8 |
11:00-13:00 |
Lunch Break |
14:30-19:00 |
Afternoon Tutorials |
C-3 |
N-1 |
V-P1 |
C-5 |
Social Event |
V-8 |
L-5/W1 |
L-W2 |
L-W3 |
14:30-16:00 |
C-4 |
N-2 |
V-3 |
C-6 |
V-P2 |
L-6 |
|
L-9 |
16:30-18:00 |
C: Computer Hardware Description Languages and Their Applications CHDL'97
N: Esprit NADA Workshop
V: VHDL Users' Forum in Europe
L: Workshop on
Libraries, Component Modelling and Quality Assurance
Fringe Meetings
- Monday, 21 April 1997 (18:30h-20:30h): IFIP WG 10.5/ECSI SIG-VHDL meeting
- Tuesday, 22 April 1997 (18:15h):
CENELEC-TC217/IEC-TC93/GUVE/AENOR ESDA Standards meeting
- Tuesday, 22 April 1997 (18:30h): IFIP WG 10.5 meeting
- Tuesday, 22 April 1997 (18:30h-22:00h): 1076.1 WG meeting
- Wednesday, 23 April 1997 (14:30h-16:30h): Presentation
Synthesizable RTL generated from a behavioral description with Visual
Architect
- Thursday, 24 April 1997 (16:30h-18:30h): CIREP/ECCI/E-CALS meeting
- Thursday, 24 April 1997 (18:30h): VLSI'97 PC meeting
- Thursday, 24 April 1997 (18:30h): CENELEC-TC217-WG2 meeting
- Thursday, 24 April 1997 (21:00h): LCMQA PC meeting
- Friday, 25 April 1997 (9:00h-13:00h): Internal NADA project meeting
chdl97@it.uc3m.es