Chair: Luc Claesen, IMEC, Belgium
E. Cerny (Programme Chair), C. Delgado Kloos (General Chair): Opening
Remarks
G. Berry: Synchronous Languages for Hardware and Software Reactive Systems
(Invited Talk) 
B. Kleinjohann, J. Tacken, Ch. Tahedl: Towards a Complete Design
Method for Embedded Systems Using Predicate/Transition-Nets Chair: Thomas Kropf, Karlsruhe Univ., Germany
F. Balarin, K. Sajid: Simplifying Data Operations for Formal Verification
K. Schneider: CTL and Equivalent Sublanguages of CTL*
R. Hojati, D. Dill, R.K. Brayton: Verifying Linear Temporal Properties
of Data Insensitive Controllers Using Finite Instantiations 
C.-T. Chou, J.-L. Huang, M. Fujita: A High-Level Language for Programming
Complex Temporal Behaviors and its Translation into Synchronous Circuits
J. Philipps, P. Scholz: System-Level Hardware Design with µ-Charts
M. Auguin, C. Belleudy, G. Gogniat: Interface Synthesis in Embedded
Hardware-Software Systems
J.-P. Soininen, J. Saarikettu, V. Veijalainen, T. Huttunen: TripleS
- A Formal Validation Environment for Functional Specifications
R.J. Machado, J.M. Fernandes, A.J. Proença: SOFHIA: A CAD Environment
to Design Digital Control Systems
A. Bardsley, D. Edwards: Compiling the Language Balsa to Delay Insensitive
Hardware
C. Mandal, R.M. Zimmer: High-Level Synthesis of Structured Data Paths
Chair: Ganesh Gopalakrishnan, Utah Univ., USA
K. Thirunarayan, R. Ewing: Charaterizing a Portable Subset of Behavioural
VHDL-93
B. Berkane, S. Gandrabur, E. Cerny: Algebra of Communicating Timing
Charts for Describing and Verifying Hardware Interfaces
F. Corella, R. Shaw, C. Zhang: A Formal Proof of Absence of Deadlock
for any Acyclic Network of PCI Buses Chair: Wolfgang Nebel, Oldenburg Univ., Germany
V. Moser, H.-P. Amann, F. Pellandini: Behavioural Modelling of Sampled-Data
with HDL-A and ABSynth 
Panel: Analog and Mixed-Signal HDLs
-
Moderator: Bart Romanowicz, EPF Lausanne, Switzerland
Panelists:- Ernst Christen, Analogy, USA
- Mark Kahrs, Rutgers Univ., USA
- Joannis Papanuskas, Bosch, Germany
- Alain Vachoux, EPF Lausanne, Switzerland
S. Raghvendra (Synopsys): Hardware Description Languages in Practical
Design Flows (Invited Talk)
J.-M. Daveau, G. Fernandes Marchioro, A.A. Jerraya: VHDL Generation
from SDL Specification 
B. Landwehr, P. Marwedel, I. Markhof, R. Dömer: Exploiting Isomorphism
for Speeding Up Binding in an Integrated Scheduling Allocation and Assignment
Approach to Architectural Synthesis (Short Talk)
Panel: The Next HDL Paradigms? -
Moderator: Carlos Delgado Kloos, Univ. Carlos III de Madrid, Spain
Panelists:- Gerard Berry, CMA, France
- Manfred Broy, Tech. Univ. München, Germany
- Stan Krolikoski, Cadence Design Systems, USA
- Wolfgang Nebel, Univ. Oldenburg, Germany
- Franz Rammig, Univ. GH Paderborn, Germany
- Srinivas Raghvendra, Synopsys, USA
Chair: Bernhard Möller, Augsburg Univ.
F. Corella: The World of I/O: A Rich Application Area for Formal Methods
(Invited Talk)
H. Barringer, D. Fellows, G. Gough, A. Williams: Abstract Modelling
of Asynchronous Micropipeline Systems using Rainbow
R. Nalumasu, G. Gopalakrishnan: A New Partial Order Reduction Algorithm
for Concurrent System Verification (Short Talk) Chair: Franz Rammig, Paderborn Univ., Germany
C. Ussery, S. Curry: Design and Verification Flows for Large Systems
in Silicon (Special Talk)
M. Heuchling, W. Ecker, M. Mrva: The Shall Design Test Development
Model for Hardware Systems
J. Mountjoy, P. Hartel, H. Corporaal: Modular Operational Semantic
Specification of Transport Triggered Architectures